Connection system of semiconductor packages using a printed circuit board

ABSTRACT

A connection system of semiconductor packages includes: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first 10 semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package includes an application processor (AP), the second semiconductor package includes a memory, and the third semiconductor package includes a power management integrated 15 circuit (PMIC).

CROSS-REFERENCE TO RELATED APPLICATION(S)

This is a Continuation Application of U.S. application Ser. No. 15/973,927 filed on May 8, 2018 in the U.S. Patent and Trademark Office, which claims benefit of priority to Korean Patent Application Nos. 10-2017-0099222 filed on Aug. 4, 2017 and 10-2017-0125425 filed on Sep. 27, 2017 in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entireties.

TECHNICAL FIELD

The present disclosure relates to a connection system of a semiconductor package, and more particularly, to a system in which a plurality of semiconductor packages are connected to each other using a printed circuit board.

BACKGROUND

Recently, in accordance with the development of smart devices, specifications of respective components thereof have been increased. Particularly, specifications of an application processor (AP), which is a core integrated circuit (IC) of the smart device, have been rapidly developed. In order to satisfy these high specifications, an AP package and a memory package have been recently used in a package-on-package (POP) manner.

Meanwhile, recently, a size of the AP package has been decreased, and the number of inputs/outputs (I/Os) of a memory has been increased. Therefore, all of the balls connected to the memory package may not only be disposed in a fan-out region of the AP package. Therefore, an interposer is disposed between the memory package and the AP package to connect the memory package and the AP package to each other or a separate backside redistribution layer is formed on a top surface of the AP package to connect the AP package to the memory package.

In addition, a power management IC (PMIC) is disposed on a printed circuit board, separately from the AP package and the memory package as described above, to manage power.

SUMMARY

An aspect of the present disclosure may provide a connection system of semiconductor packages in which an application processor (AP) and a memory may be connected to each other through a short path without using a separate interposer or backside redistribution layer and a power management IC (PMIC) may be disposed in an optimal design.

According to an aspect of the present disclosure, a connection system of semiconductor packages may be provided, in which a PMIC package and an AP package are stacked in a package-on-package (POP) form by disposing the PMIC package on the AP package, the PMIC package and the AP package stacked in POP form is mounted on one surface of a printed circuit board, and a memory package is mounted on the other surface of the printed circuit board.

According to an aspect of the present disclosure, a connection system of semiconductor packages may include: a printed circuit board; a first semiconductor package disposed on a first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on a second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures. The first semiconductor package may include an AP, the second semiconductor package may include a memory, and the third semiconductor package may include a PMIC.

BRIEF DESCRIPTION OF DRAWINGS

The above and other aspects, features, and advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system;

FIG. 2 is a schematic perspective view illustrating an example of an electronic device;

FIGS. 3A and 38 are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged;

FIG. 4 is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package;

FIG. 5 is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device;

FIG. 6 is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device;

FIG. 7 is a schematic cross-sectional view illustrating a fan-out semiconductor package;

FIG. 8 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device;

FIG. 9 is a schematic cross-sectional view illustrating a connection system of semiconductor packages according to an exemplary embodiment in the present disclosure;

FIGS. 10A through 10D are schematic cross-sectional views illustrating various examples of a first semiconductor package of the connection system of semiconductor packages of FIG. 9;

FIGS. 11A through 11F are schematic cross-sectional views illustrating various examples of a second semiconductor package of the connection system of semiconductor packages of FIG. 9;

FIGS. 12A through 12E are schematic cross-sectional views illustrating various examples of a third semiconductor package of the connection system of semiconductor packages of FIG. 9;

FIGS. 13A and 13B are schematic cross-sectional views illustrating various examples of a printed circuit board of the connection system of semiconductor packages of FIG. 9;

FIGS. 14 through 16 are schematic cross-sectional views illustrating several effects of the connection system of semiconductor packages of various examples that are in accordance with layouts of the present disclosure; and

FIG. 17 is a schematic cross-sectional view illustrating a relative problem of a connection system of semiconductor packages that is not in accordance with a layout of the present disclosure.

DETAILED DESCRIPTION

Hereinafter, exemplary embodiments in the present disclosure will be described with reference to the accompanying drawings. In the accompanying drawings, shapes, sizes, and the like, of components may be exaggerated, or stylized for clarity.

Herein, a lower side, a lower portion, a lower surface, and the like, are used to refer to a direction toward a mounting surface of the fan-out semiconductor package in relation to cross sections of the drawings, while an upper side, an upper portion, an upper surface, and the like, are used to refer to an opposite direction to the direction. However, these directions are defined for convenience of explanation, and the claims are not particularly limited by the directions defined as described above.

The meaning of a “connection” of a component to another component in the description includes an indirect connection through an adhesive layer as well as a direct connection between two components. In addition, “electrically connected” conceptually includes a physical connection and a physical disconnection. It can be understood that when an element is referred to with terms such as “first” and “second”, the element is not limited thereby. They may be used only for a purpose of distinguishing the element from the other elements, and may not limit the sequence or importance of the elements. In some cases, a first element may be referred to as a second element without departing from the scope of the claims set forth herein. Similarly, a second element may also be referred to as a first element.

The term “an exemplary embodiment” used herein does not refer to the same exemplary embodiment, and is provided to emphasize a particular feature or characteristic different from that of another exemplary embodiment. However, exemplary embodiments provided herein are considered to be able to be implemented by being combined in whole or in part with one another. For example, one element described in a particular exemplary embodiment, even if it is not described in another exemplary embodiment, may be understood as a description related to another exemplary embodiment, unless an opposite or contradictory description is provided therein.

Terms used herein are used only in order to describe an exemplary embodiment rather than limiting the present disclosure. In this case, singular forms include plural forms unless interpreted otherwise in context.

Electronic Device

FIG. 1 is a schematic block diagram illustrating an example of an electronic device system.

Referring to FIG. 1, an electronic device 1000 may accommodate a mainboard 1010 therein. The mainboard 1010 may include chip related components 1020, network related components 1030, other components 1040, and the like, physically or electrically connected thereto. These components may be connected to others to be described below to form various signal lines 1090.

The chip related components 1020 may include a memory chip such as a volatile memory (for example, a dynamic random access memory (DPAM)), a non-volatile memory (for example, a read only memory (ROM)), a flash memory, or the like; an application processor chip such as a central processor (for example, a central processing unit (CPU)), a graphics processor (for example, a graphics processing unit (GPU)), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like; and a logic chip such as an analog-to-digital (ADC) converter, an application-specific integrated circuit (ASIC), or the like. However, the chip related components 1020 are not limited thereto, and may also include other types of chip related components. In addition, the chip related components 1020 may be combined with each other.

The network related components 1030 may include protocols such as wireless fidelity (Wi-Fi) (Institute of Electrical And Electronics Engineers (IEEE) 802.11 family, or the like), worldwide interoperability for microwave access (WiMAX) (IEEE 802.16 family, or the like), EEE 802.20, long term evolution (LTE), evolution data only (Ev-DO), high speed packet access+(HSPA+), high speed downlink packet access+(HSDPA+), high speed uplink packet access+(HSUPA+), enhanced data GSM environment (EDGE), global system for mobile communications (GSM), global positioning system (GPS), general packet radio service (GPRS), code division multiple access (CDMA), time division multiple access (TDMA), digital enhanced cordless telecommunications (DECT), Bluetooth, 3G, 4G, and 5G protocols, and any other wireless and wired protocols, designated after the abovementioned protocols. However, the network related components 1030 are not limited thereto, and may also include a variety of other wireless or wired standards or protocols. In addition, the network related components 1030 may be combined with each other, together with the chip related components 1020 described above.

Other components 1040 may include a high frequency inductor, a ferrite inductor, a power inductor, ferrite beads, a low temperature co-fired ceramic (LTCC), an electromagnetic interference (EMT) filter, a multilayer ceramic capacitor (MLCC), or the like. However, other components 1040 are not limited thereto, and may also include passive components used for various other purposes, or the like. In addition, other components 1040 may be combined with each other, together with the chip related components 1020 or the network related components 1030 described above.

Depending on a type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically or electrically connected to the mainboard 1010. These other components may include, for example, a camera module 1050, an antenna 1060, a display device 1070, a battery 1080, an audio codec (not illustrated), a video codec (not illustrated), a power amplifier (not illustrated), a compass (not illustrated), an accelerometer (not illustrated), a gyroscope (not illustrated), a speaker (not illustrated), a mass storage unit (for example, a hard disk drive) (not illustrated), a compact disk (CD) drive (not illustrated), a digital versatile disk (DVD) drive (not illustrated), or the like. However, these other components are not limited thereto, and may also include other components used for various purposes depending on a type of electronic device 1000, or the like.

The electronic device 1000 may be a smartphone, a personal digital assistant (PDA), a digital video camera, a digital still camera, a network system, a computer, a monitor, a tablet PC, a laptop PC, a netbook PC, a television, a video game machine, a smartwatch, an automotive component, or the like. However, the electronic device 1000 is not limited thereto, and may be any other electronic device processing data.

FIG. 2 is a schematic perspective view illustrating an example of an electronic device.

Referring to FIG. 2, a semiconductor package may be used for various purposes in the various electronic devices 1000 as described above. For example, a motherboard 1110 may be accommodated in a body 1101 of a smartphone 1100, and various electronic components 1120 may be physically or electrically connected to the motherboard 1110. In addition, other components that may or may not be physically or electrically connected to the motherboard 1110, such as a camera module 1130, may be accommodated in the body 1101. Some of the electronic components 1120 may be the chip related components, and the semiconductor package 100 may be, for example, an application processor among the chip related components, but is not limited thereto. The electronic device is not necessarily limited to the smartphone 1100, and may be other electronic devices as described above.

Semiconductor Package

Generally, numerous fine electrical circuits are integrated in a semiconductor chip. However, the semiconductor chip may not serve as a finished semiconductor product in itself, and may be damaged due to external, physical or chemical impacts. Therefore, the semiconductor chip itself may not be used, and may be packaged and used in an electronic device, or the like, in a packaged state.

Here, semiconductor packaging is required, due to the existence of a difference in a circuit width between the semiconductor chip and a mainboard of the electronic device in terms of electrical connections. In detail, a size of connection pads of the semiconductor chip and an interval between the connection pads of the semiconductor chip are very fine, but a size of component mounting pads of the mainboard used in the electronic device and an interval between the component mounting pads of the mainboard are significantly larger than those of the semiconductor chip. Therefore, it may be difficult to directly mount the semiconductor chip on the mainboard, and packaging technology for buffering a difference in a circuit width between the semiconductor chip and the mainboard is required.

A semiconductor package manufactured by the packaging technology may be classified as a fan-in semiconductor package or a fan-out semiconductor package depending on a structure and a purpose thereof.

The fan-in semiconductor package and the fan-out semiconductor package will hereinafter be described in more detail with reference to the drawings.

Fan-in Semiconductor Package

FIGS. 3A and 33 are schematic cross-sectional views illustrating states of a fan-in semiconductor package before and after being packaged.

FIG. 4 is schematic cross-sectional views illustrating a packaging process of a fan-in semiconductor package.

Referring to FIGS. 3 and 4, a semiconductor chip 2220 may be, for example, an integrated circuit (IC) in a bare state, including a body 2221 including silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like, connection pads 2222 formed on one surface of the body 2221 and including a conductive material such as aluminum (Al), or the like, and a passivation layer 2223 such as an oxide film, a nitride film, or the like, formed on one surface of the body 2221 and covering at least portions of the connection pads 2222. In this case, since the connection pads 2222 may be significantly small, it may be difficult to mount the integrated circuit (IC) on an intermediate level printed circuit board (PCB) as well as on the mainboard of the electronic device, or the like.

Therefore, depending on a size of the semiconductor chip 2220, a connection member 2240 may be formed on the semiconductor chip 2220 in order to redistribute the connection pads 2222. The connection member 2240 may be formed by forming an insulating layer 2241 on the semiconductor chip 2220 using an insulating material such as a photoimagable dielectric (PID) resin, forming via holes 2243 h opening the connection pads 2222, and then forming wiring patterns 2242 and vias 2243. Then, a passivation layer 2250 protecting the connection member 2240 may be formed, an opening 2251 may be formed, and an underbump metal layer 2260, or the like, may be formed. That is, a fan-in semiconductor package 2200 including, for example, the semiconductor chip 2220, the connection member 2240, the passivation layer 2250, and the underbump metal layer 2260 may be manufactured through a series of processes.

As described above, the fan-in semiconductor package may have a package form in which all of the connection pads, for example, input/output (I/O) terminals, of the semiconductor chip are disposed inside the semiconductor chip, and may have excellent electrical characteristics and be produced at a low cost. Therefore, many elements mounted in smartphones have been manufactured in a fan-in semiconductor package form. In detail, many elements mounted in smartphones have been developed to implement a rapid signal transfer while having a compact size.

However, since all I/O terminals need to be disposed inside the semiconductor chip in the fan-in semiconductor package, the fan-in semiconductor package has significant spatial limitations. Therefore, it is difficult to apply this structure to a semiconductor chip having a large number of I/O terminals or a semiconductor chip having a compact size. In addition, due to the disadvantage described above, the fan-in semiconductor package may not be directly mounted and used on the mainboard of the electronic device. The reason is that even in a case in which a size of the I/O terminals of the semiconductor chip and an interval between the I/O terminals of the semiconductor chip are increased by a redistribution process, the size of the I/O terminals of the semiconductor chip and the interval between the I/O terminals of the semiconductor chip may not be sufficient to directly mount the fan-in semiconductor package on the mainboard of the electronic device.

FIG. 5 is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is mounted on an interposer substrate and is ultimately mounted on a mainboard of an electronic device.

FIG. 6 is a schematic cross-sectional view illustrating a case in which a fan-in semiconductor package is embedded in an interposer substrate and is ultimately mounted on a mainboard of an electronic device.

Referring to FIGS. 5 and 6, in a fan-in semiconductor package 2200, connection pads 2222, that is, I/O terminals, of a semiconductor chip 2220 may be redistributed through an interposer substrate 2301, and the fan-in semiconductor package 2200 may be ultimately mounted on a mainboard 2500 of an electronic device in a state in which it is mounted on the interposer substrate 2301. In this case, solder balls 2270, and the like, may be fixed by an underfill resin 2280, or the like, and an outer side of the semiconductor chip 2220 may be covered with a molding material 2290, or the like. Alternatively, a fan-in semiconductor package 2200 may be embedded in a separate interposer substrate 2302, connection pads 2222, that is, I/O terminals, of the semiconductor chip 2220 may be redistributed by the interposer substrate 2302 in a state in which the fan-in semiconductor package 2200 is embedded in the interposer substrate 2302, and the fan-in semiconductor package 2200 may be ultimately mounted on a mainboard 2500 of an electronic device.

As described above, it may be difficult to directly mount and use the fan-in semiconductor package on the mainboard of the electronic device. Therefore, the fan-in semiconductor package may be mounted on the separate interposer substrate and be then mounted on the mainboard of the electronic device through a packaging process or may be mounted and used on the mainboard of the electronic device in a state in which it is embedded in the interposer substrate.

Fan-Out Semiconductor Package

FIG. 7 is a schematic cross-sectional view illustrating a fan-out semiconductor package.

Referring to FIG. 7, in a fan-out semiconductor package 2100, for example, an outer side of a semiconductor chip 2120 may be protected by an encapsulant 2130, and connection pads 2122 of the semiconductor chip 2120 may be redistributed outwardly of the semiconductor chip 2120 by a connection member 2140. In this case, a passivation layer 2150 may further be formed on the connection member 2140, and an underbump metal layer 2160 may further be formed in openings of the passivation layer 2150. Solder balls 2170 may further be formed on the underbump metal layer 2160. The semiconductor chip 2120 may be an integrated circuit (IC) including a body 2121, the connection pads 2122, a passivation layer (not illustrated), and the like. The connection member 2140 may include an insulating layer 2141, redistribution layers 2142 formed on the insulating layer 2141, and vias 2143 electrically connecting the connection pads 2122 and the redistribution layers 2142 to each other.

As described above, the fan-out semiconductor package may have a form in which I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip. As described above, in the fan-in semiconductor package, all I/O terminals of the semiconductor chip need to be disposed inside the semiconductor chip. Therefore, when a size of the semiconductor chip is decreased, a size and a pitch of balls need to be decreased, such that a standardized ball layout may not be used in the fan-in semiconductor package. On the other hand, the fan-out semiconductor package has the form in which the I/O terminals of the semiconductor chip are redistributed and disposed outwardly of the semiconductor chip through the connection member formed on the semiconductor chip as described above. Therefore, even in a case in which a size of the semiconductor chip is decreased, a standardized ball layout may be used in the fan-out semiconductor package as it is, such that the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using a separate interposer substrate, as described below.

FIG. 8 is a schematic cross-sectional view illustrating a case in which a fan-out semiconductor package is mounted on a mainboard of an electronic device.

Referring to FIG. 8, a fan-out semiconductor package 2100 may be mounted on a mainboard 2500 of an electronic device through solder balls 2170, or the like. That is, as described above, the fan-out semiconductor package 2100 includes the connection member 2140 formed on the semiconductor chip 2120 and capable of redistributing the connection pads 2122 to a fan-out region that is outside of a size of the semiconductor chip 2120, such that the standardized ball layout may be used in the fan-out semiconductor package 2100 as it is. As a result, the fan-out semiconductor package 2100 may be mounted on the mainboard 2500 of the electronic device without using a separate interposer substrate, or the like.

As described above, since the fan-out semiconductor package may be mounted on the mainboard of the electronic device without using the separate interposer substrate, the fan-out semiconductor package may be implemented at a thickness lower than that of the fan-in semiconductor package using the interposer substrate. Therefore, the fan-out semiconductor package may be miniaturized and thinned. In addition, the fan-out semiconductor package has excellent thermal characteristics and electrical characteristics, such that it is particularly appropriate for a mobile product. Therefore, the fan-out semiconductor package may be implemented in a form more compact than that of a general package-on-package (POP) type using a printed circuit board (PCB), and may solve a problem due to the occurrence of a warpage phenomenon.

Meanwhile, the fan-out semiconductor package refers to package technology for mounting the semiconductor chip on the ma inboard of the electronic device, or the like, as described above, and protecting the semiconductor chip from external impacts, and is a concept different from that of a printed circuit board (PCB) such as an interposer substrate, or the like, having a scale, a purpose, and the like, different from those of the fan-out semiconductor package, and having the fan-in semiconductor package embedded therein.

Connection System of Semiconductor Package

FIG. 9 is a schematic cross-sectional view illustrating a connection system of semiconductor packages according to an exemplary embodiment in the present disclosure.

Referring to FIG. 9, a connection system 500 of a semiconductor package according to an exemplary embodiment in the present disclosure may include a printed circuit board 300, a first semiconductor package 100 disposed on a first surface of the printed circuit board 300, a second semiconductor package 200 disposed on a second surface of the printed circuit board 300, a third semiconductor package 400 disposed on the first semiconductor package 100, and passive components 350 disposed on the second surface of the printed circuit board 300. The first semiconductor package 100 may include an application processor (AP) 120. The second semiconductor package 200 may include a memory 220. The third semiconductor package 400 may include a power management TC (PMIC) 420. The first semiconductor package 100 may be electrically connected to the printed circuit board 300 through first electrical connection structures 170. The second semiconductor package 200 may be electrically connected to the printed circuit board 300 through second electrical connection structures 270. The third semiconductor package 400 may be electrically connected to the first semiconductor package 100 through third electrical connection structures 470.

The first semiconductor package 100 and the third semiconductor package 400 may be stacked on a package-on-package (POP) form. The first semiconductor package 100 and the third semiconductor package 400 may be electrically connected to each other through the third electrical connection structures 470 such as solder balls, or the like. For example, output power of the PMC 420 may be redistributed through a redistribution layer of the third semiconductor package 400, be connected to a redistribution layer of the first semiconductor package 100 through the third electrical connection structures 470, and be then transferred to power inputs/outputs (I/Os) of the AP 120. In addition, the second semiconductor package 200 including the memory 220 may be disposed on the second surface of the printed circuit board 300 opposing the first surface of the printed circuit board 300 on which the first semiconductor package 100 is disposed, and may be electrically connected to the first semiconductor package 100 through circuits and vias of the printed circuit board 300, such that the memory 220 and the AP 120 may transmit and receive signals therebetween. The output power of the PMIC 420 may also be connected to the memory 220 through the printed circuit board 300. The first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 300 may also be electrically connected to the passive components 350 through the printed circuit board 300.

In the connection system 500 of semiconductor packages having such a structure, the memory 220 generally has a large number of I/Os, but the second semiconductor package 200 including the memory 220 is connected to the first semiconductor package 100 through the printed circuit board 300, and the connection system 500 of semiconductor packages may not thus be affected by the number of I/Os of the memory 220. In addition, a separate backside redistribution layer or an interposer substrate is also not required, such that the connection system 500 of semiconductor packages has a large effect in terms of a cost, a yield, and the like. Therefore, the connection system 500 of a semiconductor package may be thinned, and signal paths of the connection system 500 of a semiconductor package may also be simplified. In addition, since the AP 120 and the PMIC 420 are disposed in POP form, paths of power may be significantly reduced, and since the AP 120 and the PMIC 420, generating a large amount of heat, are disposed in POP form, heat of the AP 120 and heat of the PMIC 420 may be simultaneously effectively dissipated through a design of a heat dissipation member, or the like, disposed on the third semiconductor package 400 including the PMIC 420 generating particularly the large amount of heat.

Meanwhile, as described below, the first semiconductor package 100 may be designed in a chip scale package (CSP) manner, a panel level package (PLP) manner, a wafer level package (WLP) manner, or the like, the second semiconductor package 200 may also be designed in a CSP manner, a WLP manner, a PLP manner, or the like, and the third semiconductor package 400 may also be designed in a CSP manner, a PLP manner, a WLP manner, or the like. However, the first semiconductor package 100, the second semiconductor package 200, and the third semiconductor package 400 are not limited thereto.

In addition, the passive components 350 may be multilayer ceramic capacitors (MLCCs), low inductance chip capacitors (LICCs), inductors, beads, or various known filters, or the like, respectively. The number of passive components 350 is not particularly limited, and may be more than that illustrated in the drawing or be less than that illustrated in the drawing.

In addition, the printed circuit board 300 may be the mainboard of the electronic device, and may also be a sub-board of the electronic device in some cases. The printed circuit board 300 may include a plurality of build-up layers, a plurality of circuit layers, and vias of a plurality of layers for electrical connection, and the vias of the plurality of layers may be a stack-via type in order to significantly reduce an electrical path of the first semiconductor package 100 and the second semiconductor package 200, but are not limited thereto. In some cases, a core substrate may be disposed in the printed circuit board. Other components, modules, packages, and the like, may be further mounted, in addition to the abovementioned components, on the printed circuit board 300.

FIGS. 10A through 10D are schematic cross-sectional views illustrating various examples of a first semiconductor package of the connection system of semiconductor packages of FIG. 9.

Referring to FIG. 10A, a first semiconductor package 100A according to an example may include an AP 120 having an active surface having connection pads 120P disposed thereon and an inactive surface opposing the active surface, an encapsulant 130 encapsulating at least portions of the AP 120, a connection member 140 disposed on the active surface of the AP 120 and including redistribution layers 142 a and 142 b electrically connected to the connection pads 120P of the AP 120, passivation layers 150 a and 150 b disposed on opposite surfaces of the connection member 140, an underbump metal layer 160 disposed in openings of the passivation layer 150 a and electrically connected to the redistribution layer 142 b of the connection member 140, electrical connection structures 170 electrically connected to the redistribution layer 142 b of the connection member 140 through the underbump metal layer 160, openings 131 penetrating through the encapsulant 130, and electrical connection structures 185 disposed in the opening 131. The electrical connection structures 185 may be replaced by electrical connection structures 470 of a semiconductor package 400 (400A to 400E) including a PMIC 420 to be described below. Passive components 125 may be embedded in the connection member 140. The AP 120 may be mounted on the connection member 140 through bumps 120B by surface mount technology (SMT).

The AP 120 may be an integrated circuit (IC) provided in an amount of several hundred to several million or more elements integrated in a single chip. In this case, a base material of a body of the AP may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body. The connection pads 120P may electrically connect the AP 120 to other components. A material of each of the connection pads 120P may be a conductive material such as aluminum (Al), or the like. A passivation layer exposing the connection pads 120P may be formed on the body, and may be an oxide film, a nitride film, or the like, or a double layer of an oxide layer and a nitride layer. An insulating layer, or the like, may be further disposed on each of other required positions, and an insulating layer and a redistribution layer may also be formed, if necessary. The bumps 120B for mounting the AP 120 on the connection member 140 may be disposed on the connection pads 120P. The bumps 120B may be formed of a general solder material, but are not limited thereto. The inactive surface of the AP 120 may be exposed from the encapsulant 130.

The encapsulant 130 may protect the AP 120. An encapsulation form of the encapsulant 130 is not particularly limited, and may be a form in which the encapsulant 130 surrounds at least portions of the AP 120. For example, the encapsulant 130 may cover side surfaces of the AP 120, and cover at least portions of the active surface of the AP 120. The encapsulant 130 may include an insulating material. The insulating material may be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcing material such as an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. In addition, a known molding material such as an epoxy molding compound (EMC), or the like, may also be used. Alternatively, a PID resin on which a photolithography process may be performed may also be used as the insulating material. Alternatively, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated in an inorganic filler and/or a core material such as a glass fiber (or a glass cloth or a glass fabric) may also be used as the insulating material, in order to control warpage or maintain rigidity. The openings 131 may be formed in the encapsulant 130, and the electrical connection structures 385 for POP stacking may be disposed in the openings 131. The electrical connection structures 185 may be replaced by electrical connection structures 470 to be described below.

The connection member 140 may redistribute the connection pads 120P of the AP 120. Several tens to several hundreds of connection pads 120P having various functions may be redistributed by the connection member 140, and may be physically or electrically externally connected through the electrical connection structures 170 depending on the functions. The connection member 140 may include a first insulating layer 141 a, first redistrbution layers 142 a formed on opposite surfaces of the first insulating layer 141 a, first vias 143 a penetrating through the first insulating layer 141 a and electrically connecting the first redistribution layers 142 a formed on the opposite surfaces of the first insulating layer 141 a to each other, second insulating layers 141 b formed on the opposite surfaces of the first insulating layer 141 a and covering the first redistribution layers 142 b formed on the opposite surfaces of the first insulating layer 141 a, second redistribution layers 142 b disposed on the second insulating layers 141 b formed on the opposite surfaces of the first insulating layer 141 a, and second vias 143 b penetrating through the second insulating layers 141 b formed on the opposite surfaces of the first insulating layer 141 a and electrically connecting the first redistribution layers 142 b formed on the opposite surfaces of the first insulating layer 141 a to the second redistribution layers 142 b disposed on the second insulating layers 141 b. That is, the connection member 140 may have an interposer substrate form including a core layer, but is not limited thereto. The connection member 140 may include a larger number of layers.

An insulating material may be used as a material of each of the insulating layers 141 a and 141 b. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, Ajinomoto Build up Film (ABF), FR-4, Bismaleimide Triazine (BT), or the like. Alternatively, a PID resin may also be used as the insulating material. As a non-restrictive example, the first insulating layer 141 a may include prepreg, and the second insulating layer 141 b may include ABF or PID. The first insulating layer 141 a may be used as a core layer and thus have a thickness greater than that of the second insulating layer 141 b.

The redistribution layers 142 a and 142 b may serve to substantially redistribute the connection pads 120P, and may electrically connect the connection pads 120P to each other. A material of each of the redistribution layers 142 a and 142 b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers 142 a and 142 b may perform various functions depending on designs of corresponding layers. For example, the redistribution layers 142 a and 142 b may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals with the exception of the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers 142 a and 142 b may include via pads, electrical connection structures pads, and the like.

The vias 143 a and 143 b may electrically connect the redistribution layers 142 a and 142 b, the bump 120B, or the like, formed on different layers to each other, resulting in an electrical path in the first semiconductor package 100A. A conductive material such as copper (Cu), aluminum (AI), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof, may be used as a material of each of the vias 143 a and 143 b. Each of the vias 143 a and 143 b may be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of the vias. In addition, each of the vias 143 a and 143 b may have any shape known in the related art, such as a tapered shape, a hourglass shape, a cylindrical shape, and the like. As a non-restrictive example, the first vias 143 a may have a hourglass shape, and the second vias 143 b may have a tapered shape. The first vias 143 a may have a diameter greater than that of the second vias 143 b.

The passive components 125 may be embedded in the connection member 140. The passive components 125 may be electrically connected to the second redistribution layers 142 b through the second vias 143 b in the connection member 140. The passive components 125 may be embedded type capacitors or inductors, but are not limited thereto. The passive components 125 may also be electrically connected to the connection pads 120P of the AP 120 through the redistribution layers 142 a and 142 b, the vias 143 a and 143 b, and the like.

The passivation layers 150 a and 150 b may protect the connection member 140 from external physical or chemical damage. The passivation layers 150 a and 150 b may have the openings exposing at least portions of the redistribution layer 142 b of the connection member 140. The number of openings formed in the passivation layers 150 a and 150 b may be several tens to several thousands. The passivation layers 150 a and 150 b may include an insulating resin and an inorganic filler, but may not include a glass fiber. For example, the passivation layers 150 a and 150 b may be formed of ABF, but are not limited thereto. That is, the passivation layers 150 a and 150 b may be general solder resist layers.

The underbump metal layer 160 may improve connection reliability of the electrical connection structures 170 to improve board level reliability of the first semiconductor package 100A. The underbump metal layer 160 may be connected to the redistribution layer 142 b of the connection member 140 exposed through the openings of the passivation layer 150 b. The underbump metal layer 160 may be formed in the openings of the passivation layer 150 b by any known metallization method using any known conductive material such as a metal, but is not limited thereto.

The electrical connection structures 170 may be configured to physically or electrically externally connect the first semiconductor package 100A. For example, the first semiconductor package 100A may be mounted on the printed circuit board 300 through the electrical connection structures 170. Each of the electrical connection structures 170 may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the electrical connection structures 170 is not limited thereto. Each of the electrical connection structures 170 may be a land, a ball, a pin, or the like. The electrical connection structures 170 may be formed as a multilayer or single layer structure. When the electrical connection structures 170 are formed as a multilayer structure, the electrical connection structures 170 may include a copper (Cu) pillar and a solder. When the electrical connection structures 170 are formed as a single layer structure, the electrical connection structures 170 may include a tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structures 170 are not limited thereto.

The number, an interval, a disposition form, and the like, of electrical connection structures 170 are not particularly limited, and may be sufficiently modified depending on design particulars by those skilled in the art. For example, the electrical connection structures 170 may be provided in an amount of several, tens to several thousands according to the number of connection pads 120P, or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less.

At least one of the electrical connection structures 170 may be disposed in a fan-out region. The fan-out region refers to a region with the exception of the region in which the AP 120 is disposed. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness.

The electrical connection structures 185 may be configured to electrically connect the first semiconductor package 100A to a third semiconductor package 400: 400A to 400G to be described below. Each of the electrical connection structures 185 may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the electrical connection structures 185 is not limited thereto. Each of the electrical connection structures 185 may be a land, a ball, a pin, or the like. The electrical connection structures 185 may be formed as a multilayer or single layer structure. When the electrical connection structures 185 are formed as a multilayer structure, the electrical connection structures 185 may include a copper (Cu) pillar and a solder. When the electrical connection structures 185 are formed as a single layer structure, the electrical connection structures 185 may include a tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structures 185 are not limited thereto. The electrical connection structures 185 may be replaced by electrical connection structures 470 to be described below.

Referring to FIG. 10B, a first semiconductor package 100B according to another example may include a core member 110 having a through-hole 110H, an AP 120 disposed in the through-hole of the core member 110 and having an active surface having connection pads 120P disposed thereon and an inactive surface opposing the active surface, an encapsulant 130 encapsulating at least portions of each of the core member 110 and the AP 120, a connection member 140 disposed on the core member 110 and the active surface of the AP 120 and including an insulating layer 141, redistribution layers 142, and vias 143, a passivation layer 150 disposed on the connection member 140, an underbump metal layer 160 formed in openings of the passivation layer 150 and electrically connected to the redistribution layer 142, and electrical connection structures 170 electrically connected to the underbump metal layer 160 on the underbump metal layer 160. Passive components 125 may be disposed on the passivation layer 150.

The core member 110 may include wiring layers 112 a and 112 b redistributing the connection pads 120P of the AP 120 to thus reduce the number of layers of the connection member 140. If necessary, the core member 110 may improve rigidity of the first semiconductor package 100B depending on certain materials, and serve to secure uniformity of a thickness of the encapsulant 130. The first semiconductor package 100B may be utilized as a package-on-package (POP) type package by the core member 110. The core member 110 may have the through-hole 110H. The AP 120 may be disposed in the through-hole 100H to be spaced apart from the core member 110 by a predetermined distance. Side surfaces of the AP 120 may be surrounded by the core member 110. However, such a form is only an example and may be variously modified to have other forms, and the core member 110 may perform another function depending on such a form.

The core member 110 may include an insulating layer 111, a first wiring layer 112 a disposed on a lower surface of the insulating layer 111, a second wiring layer 112 b disposed on an upper surface of the insulating layer 111, and vias 113 penetrating through the insulating layer 111 and connecting the first and second wiring layers 112 a and 112 b to each other. Thicknesses of the wiring layers 112 a and 112 b of the core member 110 may be greater than those of the redistribution layers 142 of the connection member 140. Since the core member 110 may have a thickness similar to or greater than that of the AP 120, or the like, the wiring layers 112 a and 112 b may be formed to have large sizes through a substrate process depending on a scale of the core member 110. On the other hand, the redistribution layers 142 of the connection member 140 may be formed to have small sizes, through a semiconductor process for thinness.

A material of the insulating layer 111 is not particularly limited. For example, an insulating material may be used as the material of the insulating layer ill. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a PID resin may also be used as the insulating material.

The wiring layers 112 a and 112 b may serve to redistribute the connection pads 120P of the AP 120, In addition, the wiring layers 112 a and 112 b may be used as connection patterns when the first semiconductor package 100B is used in a package-on-package (POP), or the like. A material of each of the wiring layers 112 a and 112 b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers 112 a and 112 b may perform various functions depending on designs of corresponding layers. For example, the wiring layers 112 a and 112 b may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals with the exception of the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the wiring layers 112 a and 112 b may include via pads, wire pads, connection terminal pads, and the like.

The vias 113 may electrically connect the wiring layers 112 a and 112 b formed on different layers to each other, resulting in an electrical path in the core member 110. A material of each of the vias 113 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the vias 113 may be completely filled with the conductive material, or the conductive material may be formed along a wall of each of via holes. In addition, each of the vias 113 may have any known shape such as a hourglass shape, a cylindrical shape, and the like.

The connection member 140 may redistribute the connection pads 120P of the AP 120. Several tens to several hundreds of connection pads 120P of the AP 120 having various functions may be redistributed by the connection member 140, and may be physically or electrically externally connected through the electrical connection structures 170 depending on the functions. The connection member 140 may include the insulating layers 141, the redistribution layers 142 disposed on the insulating layers 141, and the vias 143 penetrating through the insulating layers 141 and connected to the redistribution layers 142. The connection member 140 may be formed of a single layer, or may be formed of a plurality of layers of which the number is greater than that illustrated in the drawing.

A material of each of the insulating layers 141 may be an insulating material. In this case, a photosensitive insulating material such as a PID resin may also be used as the insulating material. That is, the insulating layer 141 may be a photosensitive insulating layer. When the insulating layer 141 has photosensitive properties, the insulating layer 141 may be formed to have a smaller thickness, and a fine pitch of the via 143 may be achieved more easily. The insulating layer 141 may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layers 141 are multiple layers, materials of the insulating layers 141 may be the same as each other, and may also be different from each other, if necessary. When the insulating layers 141 are the multiple layers, the insulating layers 141 may be integrated with each other depending on a process, such that a boundary therebetween may also not be apparent.

The redistribution layers 142 may serve to substantially redistribute the connection pads 120P. A material of each of the redistribution layers 142 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers 142 may perform various functions depending on designs of corresponding layers. For example, the redistribution layers 142 may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals with the exception of the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers 142 may include via pads, connection terminal pads, and the like.

The vias 143 may electrically connect the redistribution layers 142, the connection pads 120P, or the like, formed on different layers to each other, resulting in an electrical path in the first, semiconductor package 100A. A material of each of the vias 143 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the vias 143 may be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of the vias. In addition, each of the vias 143 may have any shape known in the related art such as a tapered shape.

The passive components 125 may be disposed on the passivation layer 150. The passive component 125 may be electrically connected to the redistribution layers 142 of the connection member 140. The passive components 1325 may be surface-mounted type capacitors or inductors, but are not limited thereto. The passive components 125 may also be electrically connected to the connection pads 120P of the AP 120 through the redistribution layers 142, the vias 143, and the like. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 10C, in a first semiconductor package 100C according to another example, a core member 110 may include a first insulating layer 111 a in contact with a connection member 140, a first wiring layer 112 a in contact with the connection member 140 and embedded in the first insulating layer 111 a, a second wiring layer 112 b disposed on the other surface of the first insulating layer 111 a opposing one surface of the first insulating layer 11 a in which the first wiring layer 112 a is embedded, a second insulating layer 111 b disposed on the first insulating layer 11 a and covering the second wiring layer 112 b, and a third wiring layer 112 c disposed on the second insulating layer 111 b. The first to third wiring layers 112 a, 112 b, and 112 c may be electrically connected to connection pads 120P. The first and second wiring layers 112 a and 112 b and the second and third wiring layers 112 b and 112 c may be electrically connected to each other through first, and second vias 113 a and 113 b penetrating through the first and second insulating layers 111 a and 111 b, respectively.

When the first wiring layer 112 a is embedded in the first insulating layer 111 a, a step generated due to a thickness of the first wiring layer 112 a may be significantly reduced, and an insulating distance of the connection member 140 may thus become constant, That is, a difference between a distance from a redistribution layer 142 of the connection member 140 to a lower surface of the first insulating layer 111 a and a distance from the redistribution layer 142 of the connection member 140 to the connection pad 120P of an AP 120 may be smaller than a thickness of the first wiring layer 112 a. Therefore, a high density wiring design of the connection member 140 may be easy.

A lower surface of the first wiring layer 112 a of the core member 110 may be disposed on a level above a lower surface of the connection pad 120 of the AP 120. In addition, a distance between the redistribution layer 142 of the connection member 140 and the first wiring layer 112 a of the core member 110 may be greater than that between the redistribution layer 142 of the connection member 140 and the connection pad 120P of the AP 120. The reason is that the first wiring layer 112 a may be recessed into the first insulating layer 111 a. As described above, when the first wiring layer 12 a is recessed into the first insulating layer 111 a, such that the lower surface of the first insulating layer 111 a and the lower surface of the first wiring layer 112 a have a step therebetween, a phenomenon in which a material of an encapsulant 130 bleeds to pollute the first wiring layer 112 a may be prevented. The second wiring layer 112 b of the core member 110 may be disposed on a level between an active surface and an inactive surface of the AP 120. The core member 110 may be formed at a thickness corresponding to that of the AP 120. Therefore, the second wiring layer 112 b formed in the core member 310 may be disposed on the level between the active surface and the inactive surface of the AP 120.

Thicknesses of the wiring layers 112 a, 112 b, and 112 c of the core member 110 may be greater than those of the redistribution layers 142 of the connection member 140. Since the core member 110 may have a thickness equal to or greater than that of the AP 120, the wiring layers 112 a, 112 b, and 112 c may be formed to have large sizes, depending on a scale of the core member 110. On the other hand, the redistribution layers 142 of the connection member 140 may be formed at sizes relatively smaller than those of the wiring layers 112 a, 112 b, and 112 c for thinness.

When holes for the first vias 113 a are formed, some of the pads of the first wiring layer 112 a may serve as a stopper, and it may thus be advantageous in a process that each of the first vias 113 a has the tapered shape of which a width of an upper surface is greater than that of a lower surface. In this case, the first vias 113 a may be integrated with pad patterns of the second wiring layer 112 b. In addition, when holes for the second vias 113 b are formed, some of the pads of the second wiring layer 112 b may serve as a stopper, and it may thus be advantageous in a process that each of the second vias 113 b has the tapered shape of which a width of an upper surface is greater than that of a lower surface in this case, the second vias 113 b may be integrated with pad patterns of the third wiring layer 112 c. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 10D, in a first semiconductor package 100D according to another example, a core member 110 may include a first insulating layer 111 a, a first wiring layer 112 a and a second wiring layer 112 b disposed on opposite surfaces of the first insulating layer 111 a, respectively, a second insulating layer 111 b disposed on the first insulating layer 111 a and covering the first wiring layer 112 a, a third wiring layer 112 c disposed on the second insulating layer 111 b, a third insulating layer 111 c disposed on the first insulating layer 111 a and covering the second wiring layer 112 b, and a fourth wiring layer 112 d disposed on the third insulating layer 111 c. The first to fourth wiring layers 112 a, 112 b, 112 c, and 112 d may be electrically connected to connection pads 120P. Since the core member 110 may include a large number of wiring layers 112 a, 112 b, 112 o, and 112 d, a connection member 140 may be further simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the connection member 140 may be suppressed. Meanwhile, the first to fourth wiring layers 112 a, 112 b, 112 c, and 112 d may be electrically connected to each other through first to third vias 113 a, 113 b, and 113 c penetrating through the first to third insulating layers 111 a, 111 b, and 111 c, respectively.

The first insulating layer 111 a may have a thickness greater than those of the second insulating layer 111 b and the third insulating layer 111 c. The first insulating layer 111 a may be basically relatively thick in order to maintain rigidity, and the second insulating layer 111 b and the third insulating layer 111 c may be introduced in order to form a larger number of wiring layers 112 c and 112 d. The first insulating layer 111 a may include an insulating material different from those of the second insulating layer 111 b and the third insulating layer 11.c. For example, the first insulating layer 111 a may be, for example, prepreg including a core material, a filler, and an insulating resin, and the second insulating layer 111 b and the third insulating layer 111 c may be an ABF or a PID film including a filler and an insulating resin. However, the materials of the first insulating layer 111 a and the second and third insulating layers 111 b and 111 c are not limited thereto. Similarly, the first vias 113 a penetrating through the first insulating layer 111 a may have a diameter greater than those of second vias 113 b and third vias 113 c, penetrating through the second insulating layer 111 b and the third insulating layer 111 c, respectively.

A lower surface of the third wiring layer 112 c of the core member 110 may be disposed on a level below a lower surface of the connection pad 120P of an AP 120. In addition, a distance between a redistribution layer 142 of the connection member 140 and the third wiring layer 112 c of the core member 130 may be smaller than that between the redistribution layer 142 of the connection member 140 and the connection pad 120P of the AP 120. The reason is that the third wiring layer 112 c may be disposed on the second insulating layer 111 b in protruding form, while a thin passivation layer may further be formed on the connection pad 120P of the AP 120. The first wiring layer 112 a and the second wiring layer 112 b of the core member 110 may be disposed on a level between an active surface and an inactive surface of the AP 120. Since the core member 110 may be formed at a thickness corresponding to that of the AP 120, the first wiring layer 112 a and the second wiring layer 112 b formed in the core member 110 may be disposed on the level between the active surface and the inactive surface of the AP 120.

Thicknesses of the wiring layers 112 a, 112 b, 112 c, and 112 d of the core member 110 may be greater than those of the redistribution layers 142 of the connection member 140. Since the core member 110 may have a thickness equal to or greater than that of the AP 120, the wiring layers 112 a, 212 b, 112 c, and 112 d may also be formed to have large sizes. On the other hand, the redistribution layers 142 of the connection member 140 may be formed at relatively small sizes for thinness. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

FIGS. 11A through 11F are schematic cross-sectional views illustrating various examples of a second semiconductor package of the connection system of semiconductor packages of FIG. 9.

Referring to FIG. 11A, in a second semiconductor package 200A according to an example, a plurality of memories 221 and 222 may be stacked on a connection member 240 and be encapsulated with an encapsulant 230. That is, the second semiconductor package 200A may include the connection member 240 including redistribution layers 242, a first memory 221 disposed on the connection member 240 and electrically connected to the redistribution layers 242 through bonding wires 221W, a second memory 222 disposed on the first memory 221 and electrically connected to the redistribution layers 242 through bonding wires 222W, the encapsulant 230 encapsulating at least portions of each of the first memory 221 and the second memory 222, a passivation layer 250 disposed on the connection member 240, an underbump metal layer 260 formed in openings of the passivation layer 250 and electrically connected to the redistribution layer 242, and electrical connection structures 270 electrically connected to the redistribution layer 242 through the underbump metal layer 260. The connection member 240 may be manufactured in an interposer form, but is not limited thereto. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 11B, a second semiconductor package 200B according to another example may include a core member 210 having a through-hole 210H, a first memory 221 disposed in the through-hole 210H and having an active surface having first connection pads 221P disposed thereon and an inactive surface opposing the active surface, a second memory 222 disposed on the first memory 221 in the though-hole 210H and having an active surface having second connection pads 222P disposed thereon and an inactive surface opposing the active surface, an encapsulant 230 encapsulating at least portions of the core member 210 and the first and second memories 221 and 222, and a connection member 240 disposed on the core member 210 and the active surfaces of the first and second memories 221 and 222. The second semiconductor package 200B may further include a passivation layer 250 disposed on the connection member 240, an underbump metal layer 260 formed in openings of the passivation layer 250 and electrically connected to a redistribution layer 242 of the connection member 240, and electrical connection structures 270 electrically connected to the redistribution layer 242 of the connection member 240 through the underbump metal layer 260.

The connection member 240 may include the redistribution layer 242 electrically connected to the first connection pads 221P and the second connection pads 222P. The active surface of the second memory 222 may be attached to the inactive surface of the first memory 221, and the second memory 222 may be disposed on the first memory 221 to be mismatched to the first memory 221 so that the second connection pads 222P are exposed. A phrase ‘disposed to be mismatched’ or ‘disposed to be offset’ means that side surfaces of the first memory 221 and side surfaces of the second memory 222 do not coincide with each other. The redistribution layer 242 of the connection member 240 may be connected to the first connection pads 221P and the second connection pads 222P through first vias 243 a and second vias 243 b, respectively. The second vias 243 b may be higher than the first vias 243 a.

Meanwhile, recently, a technology of stacking a plurality of memory chips in multiple stages in order to increase capacity of a memory has been developed. For example, there may be provided a technology of stacking a plurality of memory chips in two stages (or three stages), mounting the stacked memory chips on an interposer substrate, and then molding the stacked memory chips mounted on the interposer substrate using a molding material to be thus used in a package form. In this case, the stacked memory chips are electrically connected to the interposer substrate by bonding wires. However, in this structure, there is a limitation in thinness due to a significant thickness of the interposer substrate. In addition, when the interposer substrate is manufactured on the basis of silicon, significant costs may be incurred. In addition, when a reinforcing material holding the stacked memory chips is not separately included, a problem may occur in reliability due to warpage. In addition, since the stacked memory chips are electrically connected to the interposer substrate through the bonding wires, such that inputs/outputs (I/Os) are redistributed, signal paths are significantly elongated, such that signal loss may be frequently generated.

On the other hand, in a second semiconductor package 200B according to another embodiment, the core member 210 may be introduced, and a plurality of stacked memories 221 and 222 may be disposed in the through-hole 210H of the core member 210. In addition, the connection member 240 including the redistribution layers 242 may be formed, instead of introduction of the interposer substrate. Particularly, the plurality of stacked memories 221 and 222 may be connected to the redistribution layers 242 of the connection member 240 through multistage vias 243 a and 243 b having different heights rather than bonding wires. Therefore, a thickness of the connection member 240 may be significantly reduced, and a backside encapsulation thickness or a thickness of a stacked chip may also be significantly reduced. In addition, signal paths from the stacked memories 221 and 222 to the electrical connection structures 270 may be significantly reduced to reduce signal loss, resulting in improvement of signal electrical characteristics. In addition, warpage may be controlled through the core member 210, and reliability may thus be improved.

The stacked first and second memories 221 and 222 may be disposed in the through-hole 210H of the core member 210. The core member 210 may improve rigidity of the second semiconductor package 200B depending on certain materials, and serve to secure uniformity of a thickness of an encapsulant 230. Side surfaces of the stacked first and second memories 221 and 222 may be surrounded by the connection member 210. However, such a form is only an example and may be variously modified to have other forms, and the core member 210 may perform another function depending on such a form.

A material of the core member 210 is not particularly limited. For example, an insulating material may be used as the material of the core member 210. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is impregnated together with an inorganic filler in a core material, such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a PID resin may also be used as the insulating material.

The memories 221 and 222 may be an integrated circuit (IC) provided in an amount of several hundred to several million or more elements integrated in a single chip. The IC may be a memory such as a volatile memory (such as a DRAM), a non-volatile memory (such as a ROM), a flash memory, or the like, but is not limited thereto. The active surfaces of the memories 221 and 222 refer to surfaces of the memories 221 and 222 on which the connection pads 221P and 222P are disposed, and the inactive surfaces thereof refer to surfaces thereof opposing the active surfaces. The memories 221 and 222 may be formed on the basis of an active wafer. In this case, a base material of a body of each of the memories 221 and 222 may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body. The connection pads 221P and 222P may electrically connect the memories 221 and 222 to other components. A material of each of the connection pads 221P and 222P may be a conductive material such as aluminum (Al), or the like. A passivation layer exposing the connection pads 221P and 222P may be formed on each of the bodies, if necessary, and may be an oxide film, a nitride film, or the like, or a double layer of an oxide layer and a nitride layer. An insulating layer, and the like, may also be further disposed in required positions.

The memories 221 and 222 may be connected to the redistribution layers 242 of the connection member 240 through the vias 243 a and 243 b having different heights. In this case, the first vias 243 a may not penetrate through the encapsulant 230, while the second vias 243 b may penetrate through the encapsulant 230. That is, the first vias 243 a may not be in contact with the encapsulant 230, while the second vias 243 b may be in contact with the encapsulant 230. The active surface of the second memory 222 may include a first side portion facing the inactive surface of the first memory 221, a central portion facing the inactive surface of the first memory 221, and a second side portion symmetrical to the first side portion in relation to the central portion of the active surface of the second memory 222 and being at least partially out of the inactive surface of the first memory 221. In this case, the second connection pads 222P may be disposed on the second side portion of the active surface of the second memory 222. That is, the memories 221 and 222 may be disposed to be offset from each other in a step form, and the second connection pads 222P may be disposed on the second side portion of the active surface of the second memory 222, such that the multistage vias 243 a and 243 b having the different heights may be applied.

The memories 221 and 222 may be attached to each other through an adhesion member 280. The adhesion member 280 is not particularly limited, and may be a material that may attach the memories 221 and 222 to each other, such as any known tape, adhesive, or the like. In some case, the adhesion member 280 may also be omitted. Meanwhile, a disposition of the memories 221 and 222 is not limited to a form illustrated in the drawing. That is, the memories 221 and 222 may also be disposed in a form different from that illustrated in the plan view as long as they may be disposed to be offset from each other and the multistage vias 243 a and 243 b may be applied.

The encapsulant 230 may protect the memories 221 and 222. An encapsulation form of the encapsulant 230 is not particularly limited, and may be a form in which the encapsulant. 230 surrounds at least portions of the memories 221 and 222. For example, the encapsulant 230 may cover the inactive surfaces and side surfaces of the memories 221 and 222, and cover at least portions of the active surfaces of the memories 221 and 222. In addition, the encapsulant 230 may cover the core member 210, and fill at least portions of the through-bole 210H. The encapsulant 230 may include an insulating material. The insulating material may be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcing material such as an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as ABF, FR-4, BT, or the like. In addition, a known molding material such as an EMC, or the like, may also be used. Alternatively, a PID resin on which a photolithography process may be performed may also be used as the insulating material. Alternatively, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated in an inorganic filler and/or a core material such as a glass fiber (or a glass cloth or a glass fabric) may also be used as the insulating material, in order to control warpage or to maintain rigidity.

The connection member 240 may redistribute the connection pads 221P and 222P of the memories 221 and 222. In addition, the connection member 140 may electrically connect the connection pads 221P and 222P to each other. Several tens to several hundreds of connection pads 221P and 222P having various functions may be redistributed by the connection member. 240, and may be physically or electrically externally connected through the electrical connection structures 270 depending on the functions. The connection member 240 may include insulating layers 241, the redistribution layers 242 disposed on the insulating layers 241, and the vias 243 a and 243 b penetrating through the insulating layers 241 and connected to the redistribution layers 242. The connection member 240 may be formed of a single layer, or may be formed of a plurality of layers of which the number is greater than that illustrated in the drawing.

A material of each of the insulating layers 241 may be an insulating material. In this case, a photosensitive insulating material such as a PID resin may also be used as the insulating material. That is, the insulating layer 241 may be a photosensitive insulating layer. When the insulating layer 241 has photosensitive properties, the insulating layer 241 may be formed to have a smaller thickness, and a fine pitch of the via 243 may be achieved more easily. The insulating layer 241 may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layers 241 are multiple layers, materials of the insulating layers 241 may be the same as each other, and may also be different from each other, if necessary. When the insulating layers 241 are the multiple layers, the insulating layers 241 may be integrated with each other depending on a process, such that a boundary therebetween may also not be apparent.

The redistribution layers 242 may serve to substantially redistribute the connection pads 221P and 222P, and may electrically connect the connection pads 221P and 222P to each other. A material of each of the redistribution layers 242 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers 242 may perform various functions depending on designs of corresponding layers. For example, the redistribution layers 242 may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals with the exception of the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers 242 may include via pads, electrical connection structures pads, and the like.

The vias 243 a and 243 b may electrically connect the redistribution layers 242, the connection pads 221P and 222P, or the like, formed on different layers to each other, resulting in an electrical path in the second semiconductor package 2003. A material of each of the vias 243 a and 243 b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the vias 243 a and 243 b may be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of the vias. In addition, each of the vias 243 a and 243 b may have any shape known in the related art, such as a tapered shape, a cylindrical shape, and the like.

The passivation layer 250 may protect the connection member 240 from external physical or chemical damage. The passivation layer 250 may have the openings exposing at least portions of the redistribution layer 242 of the connection member 240. The number of openings formed in the passivation layer 250 may be several tens to several thousands. The passivation layer 250 may include an insulating resin and an inorganic filler, but may not include a glass fiber. For example, the passivation layer 250 may be formed of ABF, but is not limited thereto.

The underbump metal layer 260 may improve connection reliability of the electrical connection structures 270 to improve board level reliability of the second semiconductor package 2003. The underbump metal layer 260 may be connected to the redistribution layer 242 of the connection member 240 exposed through the openings of the passivation layer 250. The underbump metal layer 260 may be formed in the openings of the passivation layer 250 by any known metallization method using any known conductive material such as a metal, but is not limited thereto.

The electrical connection structures 270 may be configured to physically or electrically externally connect the second semiconductor package 200B. For example, the second semiconductor package 200B may be mounted on the printed circuit board 300 through the electrical connection structures 270. Each of the electrical connection structures 270 may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the electrical connection structures 270 is not limited thereto. Each of the electrical connection structures 270 may be a land, a ball, a pin, or the like. The electrical connection structures 270 may be formed as a multilayer or single layer structure. When the electrical connection structures 270 are formed as a multilayer structure, the electrical connection structures 270 may include a copper (Cu) pillar and a solder when the electrical connection structures 270 are formed as a single layer structure, the electrical connection structures 270 may include a tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structures 270 are not limited thereto.

The number, an interval, a disposition form, and the like, of electrical connection structures 270 are not particularly limited, and may be sufficiently modified depending on design particulars by those skilled in the art. For example, the electrical connection structures 270 may be provided in an amount of several tens to several, thousands according to the number of connection pads 221P and 222P, or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less.

At least one of the electrical connection structures 270 may be disposed in a fan-out region. The fan-out region refers to a region with the exception of the region in which the memories 221 and 222 are disposed. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 11C, in a second semiconductor package 200C according to another example, a core member 210 may include a first insulating layer 211 a in contact with a connection member 240, a first wiring layer 212 a in contact with the connection member 240 and embedded in the first insulating layer 211 a, a second wiring layer 212 b disposed on the other surface of the first insulating layer 211 a opposing one surface of the first insulating layer 211 a in which the first wiring layer 212 a is embedded, a second insulating layer 211 b disposed on the first insulating layer 211 a and covering the second wiring layer 212 b, and a third wiring layer 212 c disposed on the second insulating layer 211 b. The first to third wiring layers 212 a, 212 b, and 212 c may be electrically connected to connection pads 221P and 222P. The first and second wiring layers 212 a and 212 b and the second and third wiring layers 212 b and 212 c may be electrically connected to each other through first and second vias 213 a and 213 b penetrating through the first and second insulating layers 211 a and 211 b, respectively.

When the first wiring layer 212 a is embedded in the first insulating layer 211 a, a step generated due to a thickness of the first wiring layer 212 a may be significantly reduced, and an insulating distance of the connection member 240 may thus become constant. That is, a difference between a distance from a redistribution layer 242 of the connection member 240 to a lower surface of the first insulating layer 211 a and a distance from the redistribution layer 242 of the connection member 240 to the connection pad 221P of a memory 221 may be smaller than a thickness of the first wiring layer 212 a. Therefore, a high density wiring design of the connection member 240 may be easy.

A lower surface of the first wiring layer 212 a of the core member 210 may be disposed on a level above lower surfaces of the connection pads 221P of the memories 221. In addition, a distance between the redistribution layer 242 of the connection member 240 and the first wiring layer 212 a of the core member 210 may be greater than that between the redistribution layer 242 of the connection member 240 and the connection pad 221P of the memory 221. The reason is that the first wiring layer 212 a may be recessed into the first insulating layer 211 a. As described above, when the first wiring layer 212 a is recessed into the first insulating layer 211 a, such that the lower surface of the first insulating layer 211 a and the lower surface of the first wiring layer 212 a have a step therebetween, a phenomenon in which a material of an encapsulant 230 bleeds to pollute the first wiring layer 212 a may be prevented.

Thicknesses of the wiring layers 212 a, 212 b, and 212 c of the core member 210 may be greater than those of the redistribution layers 242 of the connection member 240. Since the core member 210 may have a thickness equal to or greater than that of the memories 221 and 222, the wiring layers 212 a, 212 b, and 212 c may be formed to have large sizes, depending on a scale of the core member 210. On the other hand, the redistribution layers 242 of the connection member 240 may be formed at sizes relatively smaller than those of the wiring layers 212 a, 212 b, and 212 c for thinness.

A material of each of the insulating layers 211 a and 211 b is not particularly limited. For example, an insulating material may be used as the material of each of the insulating layers 211 a and 211 b. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is mixed with an inorganic filler or is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a PID resin may also be used as the insulating material.

The wiring layers 212 a, 212 b, and 212 c may serve to redistribute connection pads 221P and 222P of the memories 221 and 222. A material of each of the wiring layers 212 a, 212 b, and 212 c may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers 212 a, 212 b, and 212 c may perform various functions depending on designs of corresponding layers. For example, the wiring layers 212 a, 212 b, and 212 c may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals with the exception of the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the wiring layers 212 a, 212 b, and 212 c may include via pads, wire pads, electrical connection structure pads, and the like.

The vias 213 a and 213 b may electrically connect the wiring layers 212 a, 212 b, and 212 c formed on different layers to each other, resulting in an electrical path in the core member 210. A material of each of the vias 213 a and 213 b may be a conductive material. Each of the vias 213 a and 213 b may be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of via holes. In addition, each of the vias 213 a and 213 b may have any shape known in the related art, such as a tapered shape, a cylindrical shape, and the like. When holes for the first vias 213 a are formed, some of the pads of the first wiring layer 212 a may serve as a stopper, and it may thus be advantageous in a process that each of the first vias 213 a has the tapered shape of which a width of an upper surface is greater than that of a lower surface. In this case, the first vias 213 a may be integrated with pad patterns of the second wiring layer 212 b. In addition, when holes for the second vias 213 b are formed, some of the pads of the second wiring layer 212 b may serve as a stopper, and it may thus be advantageous in a process that each of the second vias 213 b has the tapered shape of which a width of an upper surface is greater than that of a lower surface, in this case, the second vias 213 b may be integrated with pad patterns of the third wiring layer 212 c. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 110, in a second semiconductor package 200D according to another example, a core member 210 may include a first insulating layer 211 a, a first wiring layer 212 a and a second wiring layer 212 b disposed on opposite surfaces of the first insulating layer 211 a, respectively, a second insulating layer 211 b disposed on the first insulating layer 211 a and covering the first wiring layer 212 a, a third wiring layer 212 c disposed on the second insulating layer 211 b, a third insulating layer 211 c disposed on the first insulating layer 211 a and covering the second wiring layer 212 b, and a fourth wiring layer 212 d disposed on the third insulating layer 211 c. The first to fourth wiring layers 212 a, 212 b, 212 c, and 212 d may be electrically connected to connection pads 221P and 222P. Since the core member 210 may include a large number of wiring layers 212 a, 212 b, 212 c, and 212 d, a connection member 240 may be further simplified. Therefore, a decrease in a yield depending on a defect occurring in a process of forming the connection member 240 may be suppressed. Meanwhile, the first to fourth wiring layers 212 a, 212 b, 212 c, and 212 d may be electrically connected to each other through first to third vias 213 a, 213 b, and 213 c penetrating through the first to third insulating layers 211 a, 211 b, and 211 c, respectively.

The first insulating layer 211 a may have a thickness greater than those of the second insulating layer 211 b and the third insulating layer 211 c. The first insulating layer 211 a may basically be relatively thick in order to maintain rigidity, and the second insulating layer 211 b and the third insulating layer 211 c may be introduced in order to form a larger number of wiring layers 212 c and 212 d. The first insulating layer 211 a may include an insulating material different from those of the second insulating layer 211 b and the third insulating layer 211 c. For example, the first insulating layer 211 a may be, for example, prepreg including a core material, a filler, and an insulating resin, and the second insulating layer 211 b and the third insulating layer 211 c may be an ABF or a PID film including a filler and an insulating resin. However, the materials of the first insulating layer 211 a and the second and third insulating layers 211 b and 211 c are not limited thereto. Similarly, the first vias 213 a penetrating through the first insulating layer 211 a may have a diameter greater than those of second vias 213 b and third vias 213 c penetrating through the second insulating layer 211 b and the third insulating layer 211 c, respectively.

A lower surface of the third wiring layer 212 c of the core member 210 may be disposed on a level below a lower surface of the connection pad 221P of a memory 222. In addition, a distance between a redistribution layer 242 of the connection member 240 and the third wiring layer 212 c of the core member 210 may be greater than those between the redistribution layer 242 of the connection member 240 and the connection pads 221P and 222P of the memories 221 and 222. The reason is that the third wiring layer 212 c may be disposed on the second insulating layer 211 b in protruding form, while a thin passivation layer may further be formed on the connection pads 221P of the memory 221.

Thicknesses of the wiring layers 212 a, 212 b, 212 c, and 212 d of the core member 210 may be greater than those of the redistribution layers 242 of the connection member 240. Since the core member 210 may have a thickness equal to or greater than that of the memories 221 and 222, the wiring layers 212 a, 212 b, 212 c, and 212 d may be formed to have large sizes. On the other hand, the redistribution layers 242 of the connection member 240 may be formed at relatively small sizes for thinness. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 11E, a second semiconductor package 200E according to another example may be substantially the same as the second semiconductor package 200B illustrated in FIG. 11B except that a horizontal cross-sectional area of a second memory 222 is greater than that of a first memory 221. That is, an active surface of the second memory 222 may be wider than an inactive surface of the first memory 221. In this case, the active surface of the second memory 222 may include a first side portion being at least partially outside of the inactive surface of the first memory 221, a central portion facing the inactive surface of the first memory 221, and a second side portion symmetrical to the first side portion in relation to the central portion and being at least partially out of the inactive surface of the first memory 221, and second connection pads 222P may be disposed on both of the first and second side portions of the active surface of the second memory 222. That is, the memories 221 and 222 may be disposed to be offset from each other in a form in which they have different horizontal cross-sectional areas, and the second connection pads 222P may be disposed on the first and second side portions of the active surface of the second memory 222, such that multistage vias 243 a and 243 b may be applied. Other configurations overlap those described above, and a detailed description thereof is thus omitted. Meanwhile, the core member 210 illustrated in FIGS. 11C and 11D may also be used in the second semiconductor package 200E.

Referring to FIG. 11F, a second semiconductor package 200F according to another example may be substantially the same as the second semiconductor package 200B illustrated in FIG. 111 except that it further includes a third memory 223 disposed side by side with a first memory 221 in a through-hole 210H and having an active surface having third connection pads 223P disposed thereon and an inactive surface opposing the active surface and a fourth memory 224 disposed on the third memory 223 in the through-hole 210H and having an active surface having fourth connection pads 224P disposed thereon and an inactive surface opposing the active surface. The active surface of the fourth memory 224 may be attached to the inactive surface of the third memory 223, and the fourth memory 224 may be disposed on the third memory 223 to be mismatched to the third memory 223 in a kind of step form so that the fourth connection pads 224P are exposed. A redistribution layer 242 of a connection member 240 may be connected to the third connection pads 223P and the fourth connection pads 224P through first vias 243 a and second vias 243 b, respectively. As described above, even in a structure in which the memories 221, 222, 223, and 224 are connected to each other in a two-stage parallel structure, multistage vias 243 a and 243 b may be applied. The first and second memories 221 and 222 and the third and fourth memories 223 and 224 may be connected to each other through first and second adhesion members 280 a and 280 b, respectively. Other configurations overlap those described above, and a detailed description thereof is thus omitted. Meanwhile, the core member 210 illustrated in FIGS. 11C and 11D may also be used in the second semiconductor package 200F.

FIGS. 12A through 12E are schematic cross-sectional views illustrating various examples of a third semiconductor package of the connection system of semiconductor packages of FIG. 9.

Referring to FIG. 12A, a third semiconductor package 400A according to an example may include a PMIC 420 having an active surface having connection pads 420P disposed thereon and an inactive surface opposing the active surface, an encapsulant 430 encapsulating at least portions of the PMIC 420, a connection member 440 disposed on the active surface of the PMIC 420 and including insulating layers 441 and redistribution layers 442 and vias 443 formed on and in the insulating layers 441, a passivation layer 450 disposed on the connection member 440, an underbump metal layer 460 disposed in openings of the passivation layer 450 and electrically connected to the redistribution layer 442 of the connection member 440, and electrical connection structures 470 electrically connected to the redistribution layer 442 of the connection member 440 through the underbump metal layer 460.

The PMIC 420 may be an IC provided in an amount of several hundred to several million or more elements integrated in a single chip. In this case, a base material of a body of the PMIC may be silicon (Si), germanium (Ge), gallium arsenide (GaAs), or the like. Various circuits may be formed on the body. The connection pads 420P may electrically connect the PMIC 420 to other components. A material of each of the connection pads 420P may be a conductive material such as aluminum (Al), or the like. A passivation layer exposing the connection pads 420P may be formed on the body, and may be an oxide film, a nitride film, or the like, or a double layer of an oxide layer and a nitride layer. An insulating layer, or the like, may be further disposed on each of other required positions, and an insulating layer and a redistribution layer may also be formed, if necessary.

The encapsulant 430 may protect the PMIC 420. An encapsulation form of the encapsulant 430 is not particularly limited, and may be a form in which the encapsulant 430 surrounds at least portions of the PMIC 420. For example, the encapsulant 430 may cover the inactive surface and side surfaces of the PMIC 420, and cover at least portions of the active surface of the PMIC 420. The encapsulant 430 may include an insulating material. The insulating material may be a material including an inorganic filler and an insulating resin, for example, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin having a reinforcing material such as an inorganic filler impregnated in the thermosetting resin and the thermoplastic resin, such as ABF, FR-4, BT, or the like. In addition, any known molding material such as an EMC, or the like, may also be used. Alternatively, a PID resin on which a photolithography process may be performed may also be used as the insulating material. Alternatively, a material in which an insulating resin such as a thermosetting resin or a thermoplastic resin is impregnated in an inorganic filler and/or a core material such as a glass fiber (or a glass cloth or a glass fabric) may also be used as the insulating material, in order to control warpage or maintain rigidity.

The connection member 440 may redistribute the connection pads 420P of the PMIC 420. Several tens to several hundreds of connection pads 420P having various functions may be redistributed by the connection member 440, and may be physically or electrically externally connected through the electrical connection structures 470 depending on functions. The connection member 440 may include the insulating layers 441, the redistribution layers 442 disposed on the insulating layers 441, and the vias 443 penetrating through the insulating layers 441 and connected to the redistribution layers 442. The connection member 440 may be formed of a single layer, or may be formed of a plurality of layers of which the number is greater than that, illustrated in the drawing.

A material of each of the insulating layers 441 may be an insulating material. In this case, a photosensitive insulating material such as a PID resin may also be used as the insulating material. That is, the insulating layer 441 may be a photosensitive insulating layer. When the insulating layer 441 has photosensitive properties, the insulating layer 441 may be formed to have a smaller thickness, and a fine pitch of the via 443 may be achieved more easily. The insulating layer 441 may be a photosensitive insulating layer including an insulating resin and an inorganic filler. When the insulating layers 441 are multiple layers, materials of the insulating layers 441 may be the same as each other, and may also be different from each other, if necessary. When the insulating layers 441 are the multiple layers, the insulating layers 441 may be integrated with each other depending on a process, such that a boundary therebetween may also not be apparent.

The redistribution layers 442 may serve to substantially redistribute the connection pads 420P, and may electrically connect the connection pads 420P to each other, A material of each of the redistribution layers 44:2 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The redistribution layers 442 may perform various functions depending on designs of corresponding layers. For example, the redistribution layers 442 may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals with the exception of the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the redistribution layers 442 may include via pads, electrical connection structures pads, and the like.

The vias 443 may electrically connect the redistribution layers 442, the connection pads 420P, or the like, formed on different layers to each other, resulting in an electrical path in the third semiconductor package 400A. A material of each of the vias 443 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (TI), or alloys thereof. Each of the vias 443 may be completely filled with the conductive material, or the conductive material may also be formed along a wall of each of the vias. In addition, each of the vias 443 may have any shape known in the related art, such as a tapered shape, a cylindrical shape, and the like.

A heat dissipation member 440B may be formed on a region of the connection member 440 connected to the active surface of the PMIC 420, if necessary. The heat dissipation member 440B may include heat dissipation vias of a plurality of layers densely formed at a very short distance, but is not limited thereto, and may include metal blocks, or the like, instead of the heat dissipation vias. When the heat dissipation member 440B is formed, heat of the PMIC 420 generating a large amount of heat may be more effectively dissipated, and the third semiconductor package 400A may thus have an excellent heat dissipation effect.

The passivation layer 450 may protect the connection member 440 from external physical or chemical damage. The passivation layer 450 may have the openings exposing at least portions of the redistribution layer 442 of the connection member 440. The number of openings formed in the passivation layer 450 may be several tens to several thousands. The passivation layer 450 may include an insulating resin and an inorganic filler, but may not include a glass fiber. For example, the passivation layer 450 may be formed of ABF, but is not limited thereto.

The underbump metal layer 460 may improve connection reliability of the electrical connection structures 470 to improve board level reliability of the third semiconductor package 400A. The underbump metal layer 460 may be connected to the redistribution layer 442 of the connection member 440 exposed through the openings of the passivation layer 450. The underbump metal layer 460 may be formed in the openings of the passivation layer 450 by any known metallization method using any known conductive material such as a metal, but is not limited thereto.

The electrical connection structures 470 may be additionally configured to physically or electrically externally connect the third semiconductor package 400A. For example, the third semiconductor package 400A may be mounted on the printed circuit board 300 through the electrical connection structures 470. Each of the electrical connection structures 470 may be formed of a conductive material, for example, a solder, or the like. However, this is only an example, and a material of each of the electrical connection structures 470 is not limited thereto. Each of the electrical connection structures 470 may be a land, a ball, a pin, or the like. The electrical connection structures 470 may be formed as a multilayer or single layer structure. When the electrical connection structures 470 are formed as a multilayer structure, the electrical connection structures 470 may include a copper (Cu) pillar and a solder. When the electrical connection structures 470 are formed as a single layer structure, the electrical connection structures 470 may include a tin-silver solder or copper (Cu). However, this is only an example, and the electrical connection structures 470 are not limited thereto.

The number, an interval, a disposition form, and the like, of electrical connection structures 470 are not particularly limited, and may be sufficiently modified depending on design particulars by those skilled in the art. For example, the electrical connection structures 470 may be provided in an amount, of several tens to several thousands according to the number of connection pads 420P, or may be provided in an amount of several tens to several thousands or more or several tens to several thousands or less.

At least one of the electrical connection structures 470 may be disposed in a fan-out region. The fan-out region refers to a region with the exception of the region in which the PMIC 420 is disposed. The fan-out package may have excellent reliability as compared to a fan-in package, may implement a plurality of input/output (I/O) terminals, and may facilitate a 3D interconnection. In addition, as compared to a ball grid array (BGA) package, a land grid array (LGA) package, or the like, the fan-out package may be manufactured to have a small thickness, and may have price competitiveness. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 12B, a third semiconductor package 400B according to another example may further include a core member 410 having a through-hole 410H. A PMIC 420 may be disposed in the through-hole 410H of the core member 410. The core member 410 may improve rigidity of the third semiconductor package 400B depending on certain materials, and serve to secure uniformity of a thickness of an encapsulant 430. Side surfaces of the PMIC 420 may be surrounded by the core member 410. However, such a form is only an example and may be variously modified to have other forms, and the core member 410 may perform another function depending on such a form.

A material of the core member 410 is not particularly limited. For example, an insulating material may be used as the material of the core member 410. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a PID resin may also be used as the insulating material. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 12C, a third semiconductor package 400C according to another example may further include passive components 425 disposed side by side with a PMIC 420 and at least partially encapsulated by an encapsulant 430. The passive components 425 may be electrically connected to connection pads 420P of the PMIC 420 through a redistribution layer 44:2 of a connection member 440. The passive components 425 may be embedded type or surface-mounted type capacitors or inductors, but are not limited thereto. The number of passive components 425 is not particularly limited, and may be changed depending on kinds and thicknesses of passive components. When the passive components 425 are disposed together with the PMIC 420, the number of separate passive components disposed on a printed circuit board 300: 300A and 3008 may be significantly reduced. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 12D, a third semiconductor package 400D according to another example may further include a core member 410 having a through-hole 410H. In addition, the third semiconductor package 400D may further include passive components 425 disposed side by side with a PMIC 420 in the through-hole 410H and at least partially encapsulated by an encapsulant 430. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

Referring to FIG. 12E, a third semiconductor package 400E according to another example may further include a core member 410 having a through-hole 410H. In addition, the third semiconductor package 400E may further include passive components 425 disposed side by side with a PMIC 420 in the through-hole 410H and at least partially encapsulated by an encapsulant 430. Here, the core member 410 may include wiring layers 412 a and 412 b redistributing connection pads 420P of the PMIC 420, and include an underbump metal layer 460 and electrical connection structures 460 formed on the wiring layer 412 b. That is, in the third semiconductor package 400E according to another example, the PMIC 420 and the passive components 425 may be disposed in face-up form in relation to the third semiconductor package 400E, and may be electrically connected to the electrical connection structures 470 through a connection member 440 and the core member 410. That is, the electrical connection structures 470 may be disposed on the other surface of the core member 410 opposing one surface of the core member 410 on which the connection member 440 is disposed, and may be electrically connected to the wiring layer 412 b through the underbump metal, layer 460, and the like. Heat of the PMIC 420 may be more effectively dissipated externally from an opened space through such a disposition form.

The core member 410 may include an insulating layer 411, a first wiring layer 412 a disposed on a lower surface of the insulating layer 411, a second wiring layer 412 b disposed on an upper surface of the insulating layer 411, and vias 413 penetrating through the insulating layer 411 and connecting the first and second wiring layers 412 a and 412 b to each other. Thicknesses of the wiring layers 412 a and 412 b of the core member 410 may be greater than those of redistribution layers 442 of the connection member 440. Since the core member 410 may have a thickness similar to or greater than that of the PMIC 420, or the like, the wiring layers 412 a and 412 b may be formed to have large sizes through a substrate process depending on a scale of the core member 410. On the other hand, the redistribution layers 442 of the connection member 440 may be formed to have small sizes, through a semiconductor process for thinness.

A material of the insulating layer 411 is not particularly limited. For example, an insulating material may be used as the material of the insulating layer 411. In this case, the insulating material may be a thermosetting resin such as an epoxy resin, a thermoplastic resin such as a polyimide resin, a resin in which the thermosetting resin or the thermoplastic resin is impregnated together with an inorganic filler in a core material such as a glass fiber (or a glass cloth or a glass fabric), for example, prepreg, ABF, FR-4, BT, or the like. Alternatively, a PID resin may also be used as the insulating material.

The wiring layers 412 a and 412 b may serve to redistribute the connection pads 420P of the PMIC 420. In addition, the wiring layers 412 a and 412 b may be used as connection patterns when the third semiconductor package 400E is used in a POP, or the like. A material of each of the wiring layers 412 a and 412 b may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. The wiring layers 412 a and 412 b may perform various functions depending on designs of corresponding layers. For example, the wiring layers 412 a and 412 b may include ground (GND) patterns, power (PWR) patterns, signal (S) patterns, and the like. Here, the signal (S) patterns may include various signals with the exception of the ground (GND) patterns, the power (PWR) patterns, and the like, such as data signals, and the like. In addition, the wiring layers 412 a and 412 b may include via pads, wire pads, connection terminal pads, and the like.

The vias 413 may electrically connect the wiring layers 412 a and 412 b formed on different layers to each other, resulting in an electrical path in the core member 410. A material of each of the vias 413 may be a conductive material such as copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or alloys thereof. Each of the vias 413 may be completely filled with the conductive material, or the conductive material may be formed along a wall of each of via holes. In addition, each of the vias 413 may have any known shape such as an hourglass shape, a cylindrical shape, and the like. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

FIGS. 13A and 13B are schematic cross-sectional views illustrating various examples of a printed circuit board of the connection system of semiconductor packages of FIG. 9.

Referring to FIG. 13A, a printed circuit board 300A according to an example may have a form of a coreless substrate 320 having passivation layers 330 and 340 formed, respectively, on opposite surfaces thereof. In more detail, the printed circuit board 300A may have a form in which in which the passivation layers 330 and 340 are formed, respectively, on the opposite surfaces of the coreless substrate 320 including an insulating layer 321 formed by stacking a plurality of build-up layers, a plurality of circuit layers 322 formed on the respective build-up layers, and a plurality of via layers 323 penetrating through the respective build-up layers to connect the circuit layers 322 to each other. A material of each of the build-up layers of the insulating layer 321 may be any known insulating material such as epoxy, polyimide, or the like, together with an inorganic filler, and a material of each of the circuit layers 322 and the via layers 323 may be any known conductive material such as copper (Cu), or the like. A material of each of the passivation layers 330 and 340 may be a solder resist, or the like. However, the materials of the build-up layers, the circuit layers 322 and the via layers 323, and the passivation layers 330 and 340 are not limited thereto. Various components may be embedded in the printed circuit board 300A, if necessary.

Referring to FIG. 13B, a printed circuit board 3008 according to another example may have a form of a core substrate in which build-up members 320 a and 320 b are disposed on opposite surfaces of a core member 310, respectively, and passivation layers 330 and 340 are disposed on the build-up members 320 a and 320 b, respectively. The core member 310 may include a core layer 311, circuit layers 312 formed on opposite surfaces of the core layer 311, respectively, and through-wirings 313 penetrating through the core layer 311. The respective build-up members 320 a and 320 b may include build-up layers 321 a and 321 b, circuit layers 322 a and 322 b each formed on the build-up layers 321 a and 321 b, and via layers 323 a and 323 b each penetrating through the build-up layers 321 a and 321 b, respectively. A larger number of layers may also be formed. The core layer 311 may be introduced through a copper clad laminate (CCL), or the like, and may be formed of prepreg, or the like, but is not limited thereto. Other configurations overlap those described above, and a detailed description thereof is thus omitted.

FIGS. 14 through 16 are schematic cross-sectional views illustrating several effects of the connection system of semiconductor packages of various examples that are in accordance with layouts of the present disclosure.

Referring to FIG. 14, in a connection system 500A of semiconductor packages according to an example, the memory 220 of the second semiconductor package 200F described above is disposed vertically below the AP 120 of the first semiconductor package 1008 described above in relation to the printed circuit board 300A, and transfer paths of signals S may thus be significantly reduced, and the third semiconductor package 400B described above is disposed in POP form above the AP 120 of the first semiconductor package 100B described above, and transfer paths of power P may thus be optimized. In addition, in such a POP disposition form, a shield can 620 may be attached to the third semiconductor package 400B using the known resin layer 610, and a heat pipe 630 may be disposed on the shield can 620 to simultaneously lower effectively heat of the AP 120 and the PMIC 420 generating a large amount of heat. Other paths of power P may pass through passive components 350 mounted on the printed circuit board 300A.

Referring to FIG. 15, in a connection system 500 of semiconductor packages according to another example, the memory 220 of the second semiconductor package 200F described above is disposed directly below the AP 120 of the first semiconductor package 100B described above in relation to the printed circuit board 300A, and transfer paths of signals S may thus be significantly reduced, and the third semiconductor package 400D described above is disposed in POP form above the AP 120 of the first semiconductor package 100B described above, and transfer paths of power P may thus be optimized. In addition, in such a POP disposition form, a shield can 620 may be attached to the third semiconductor package 400B using the known resin layer 610, and a heat pipe 630 may be disposed on the shield can 620 to simultaneously lower effectively heat H of the AP 120 and the PMIC 420 generating a large amount of heat. Particularly, the third semiconductor package 400D includes the passive components 425 passing through paths of power P, and the number of passive components 350 mounted on the printed circuit board 300A may be significantly reduced.

Referring to FIG. 16, in a connection system 500E of semiconductor packages according to another example, the memory 220 of the second semiconductor package 200F described above is disposed directly below the AP 120 of the first semiconductor package 100B described above in relation to the printed circuit board 300A, and transfer paths of signals S may thus be significantly reduced, and the third semiconductor package 400E described above is disposed in POP form above the AP 120 of the first semiconductor package 100B described above, and transfer paths of power P may thus be optimized. In addition, in such a POP disposition form, a shield can 620 may be attached to the third semiconductor package 400B using the known resin layer 610, and a heat pipe 630 may be disposed on the shield can 620 to simultaneously lower effectively heat of the AP 120 and the PMIC 420 generating a large amount of heat. Particularly, in the third semiconductor package 400E, the PMIC 420 may be disposed in face-up form. Therefore, heat H may be more effectively transferred to the heat pipe 630 through a heat dissipation member 440B formed in the connection member 440. That is, a heat dissipation effect on heat generated in the PMIC 420, and the like, may be very excellent.

FIG. 17 is a schematic cross-sectional view illustrating a relative problem of a connection system of semiconductor packages that is not in accordance with a layout of the present disclosure.

Referring to the drawings, in a connection system 700 of a semiconductor package that is not in accordance with the present disclosure, a memory package 730 may be disposed on an AP package 710 in POP form with an interposer 720 interposed therebetween, and such a POP structure may be disposed on one surface of a printed circuit board 740. In addition, a PMIC package 750 and passive components 760 may be disposed on the other surface of the printed circuit board 740. In such a structure, an AP and a PMIC are far from each other, such that a complicated structure for heat dissipation is required and transfer paths of signals S and power P are increased.

As set forth above, according to the exemplary embodiments in the present disclosure, a connection system of semiconductor packages in which an AP and a memory may be connected to each other through a short path without using a separate interposer or backside redistribution layer and a PMIC may be disposed in an optimal design may be provided.

While exemplary embodiments have been shown and described above, it will be apparent to those skilled in the art that modifications and variations could be made without departing from the scope of the present invention as defined by the appended claims. 

What is claimed is:
 1. A connection system of semiconductor packages, comprising: a printed circuit board having a first surface and a second surface opposing the first surface; a first semiconductor package disposed on the first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on the second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; and a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures, wherein the first semiconductor package includes: an application processor (AP) having an active surface having connection pads disposed thereon, and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the AP; a connection member disposed on the active surface of the AP and including a redistribution layer electrically connected to the connection pads of the AP; and conductive structures vertically passing through at least a portion of the encapsulant and electrically connecting the redistribution layer of the connection member and the third electrical connection structures, wherein the second semiconductor package includes a first memory.
 2. The connection system of semiconductor packages of claim 1, wherein the first semiconductor package and the second semiconductor package are disposed to face each other with the printed circuit board interposed therebetween.
 3. The connection system of semiconductor packages of claim 1, wherein the first semiconductor package further includes openings penetrating through the encapsulant and exposing at least portions of each of the conductive structures, and wherein the third electrical connection structures are disposed in the openings of the encapsulant.
 4. The connection system of semiconductor packages of claim 1, wherein each of the third electrical connection structures is directly disposed on each of the conductive structures.
 5. The connection system of semiconductor packages of claim 1, wherein the second semiconductor package further includes a second memory disposed on the first memory.
 6. The connection system of semiconductor packages of claim 5, the first memory and the second memory are staggered to each other.
 7. The connection system of semiconductor packages of claim 5, wherein the second semiconductor package further includes an adhesion member attaching the first memory and the second memory to each other.
 8. The connection system of semiconductor packages of claim 1, wherein the second semiconductor package further includes a second memory disposed side by side with the first memory.
 9. The connection system of semiconductor packages of claim 8, wherein the second memory is spaced apart from the first memory.
 10. The connection system of semiconductor packages of claim 1, wherein the third semiconductor package includes a power management integrated circuit (PMIC) having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface, an encapsulant encapsulating at least portions of the PMIC, a connection member disposed on the active surface of the PMIC and including a redistribution layer electrically connecting the connection pads of the PMIC, and the third electrical connection structures.
 11. The connection system of semiconductor packages of claim 10, wherein the third semiconductor package further includes passive components disposed side by side with the PMIC on one surface of the connection member on which the PMIC is disposed and at least partially encapsulated by the encapsulant.
 12. The connection system of semiconductor packages of claim 1, further comprising a plurality of passive components disposed on the second surface of the printed circuit board.
 13. The connection system of semiconductor packages of claim 1, further comprising a heat pipe disposed on the third semiconductor package.
 14. The connection system of semiconductor packages of claim 1, wherein the printed circuit board is a mainboard or a sub-board of an electronic device.
 15. The connection system of semiconductor packages of claim 1, wherein the third semiconductor package includes a power management integrated circuit (PMIC), and wherein output power of the power management integrated circuit (PMIC) is connected to the first memory through the conductive structures and the printed circuit board.
 16. A connection system of semiconductor packages, comprising: a printed circuit board having a first surface and a second surface opposing the first surface and including a plurality of circuit layers; a first semiconductor package disposed on the first surface of the printed circuit board and connected to the printed circuit board through first electrical connection structures; a second semiconductor package disposed on the second surface of the printed circuit board and connected to the printed circuit board through second electrical connection structures; a third semiconductor package disposed on the first semiconductor package and connected to the first semiconductor package through third electrical connection structures, and a heat pipe disposed on the third semiconductor package.
 17. The connection system of semiconductor packages of claim 16, wherein the first semiconductor package includes a plurality of redistribution layers facing the plurality of circuit layers of the printed circuit board.
 18. The connection system of semiconductor packages of claim 16, further comprising a shield can disposed between the third semiconductor package and the heat pipe.
 19. The connection system of semiconductor packages of claim 18, wherein the shield can is attached to the third semiconductor package by a resin layer.
 20. The connection system of semiconductor packages of claim 16, further comprising connection pads interposed between the second semiconductor package and the second surface of the printed circuit board. 